High performance of a graphics controller within a computer system is important for achieving high interactivity of the system. To reduce access time when reading from memory, concurrency is often designed into the circuitry between a processor (CPU) and a bank of memory. Usually, this concurrency is implemented exclusively in the circuit or circuits responsible for the control of the memory, and not in the circuit that interfaces the CPU to the memory.
When accessing certain types of memory, indirect addressing may be used. Indirect addressing often involves an indirect address register which is used to actually address the memory. To use indirect addressing, first the CPU stores a memory address in the indirect address register. The CPU then issues indirect read or write commands, which do not contain a memory address. When the memory controller receives an indirect read or write command, it returns/stores data from/to a memory location at the address stored in the indirect address register, and then increments or decrements the indirect address register in preparation for the next indirect read or write. The indirect address register is incremented or decremented by a fixed amount, typically the number of bytes read or written during the indirect read or write.
Memory controllers are sometimes designed to pre-fetch a number of bytes from the memory wherein the addresses of the bytes are adjacent to the byte currently being read using the indirect read address register. This "read ahead" behavior of the controller overlaps the read cycle time of the memory with the time required for the memory controller to send the data to the interface.
In typical graphic device controllers, however, there is an additional frame buffer data bus connecting the CPU interface controller and the frame buffer (memory) controller contained within the graphics device controller. The read ahead within the frame buffer controller does not improve performance over this frame buffer data bus.
It is thus apparent that there is a need in the art for an improved method or apparatus which achieves read concurrency within a graphics controller device. There is a further need for such a method of apparatus that improves performance over the frame buffer data bus between the frame buffer controller and the CPU interface controller within the graphics device controller. The present invention meets these and other needs in the art.